The present invention generally relates to data processing systems and more particularly to processors utilized for servicing communication lines.
A programmable communications processor can be described as a digital computer which is peripheral to another data processing computer and which is programmed to perform operational and interface requirements of a data communications network. With the communications processor performing data communications functions, the entire data processing system may be made to be quite flexible and adaptable despite changes in communications requirements. Data communications processors, controllers or adaptors have been said to be programmable and in many cases have been to various degrees. Some such programmable devices are programmed through switches, and others permit the central processor programs to set up the various parameters of the communications lines. Some such communications processors utilize a somewhat standard central processor to provide a front-end to another central processor thereby achieving programmability and some flexibility, usually at the expense of added cost. It is desirable that the communications control unit or communications processor be programmable to the maximum extent possible thereby providing flexibility and adaptability independent of the changing conditions in the system, including the various communications line disciplines which may be encountered. It is therefore desirable to include mechanisms by which programs are allowed to execute in the communications processors, thereby enabling control of the various lines including the check of status changes and manipulation of data and the loading, receiving or transmitting of such data between the communications lines and the main memory of the system. It is further desirable to enable such programming control included in the communications processor to control the speed and various identification bits such as stop, mark, space and synchronous bits, as well as to service various control characters and bits and parity indications. It is further desirable to include a mechanism for the orderly execution of a variety of such programs to control the transfer of data over the communications lines, and to react to interrupt conditions.
One of the major bottlenecks in a communications system can be the interface to the main memory and the control of the data transfer thereto. Systems have been designed in the past which require the memory access for every byte or portion of a byte received. It is accordingly desirable to improve the speed of the system by providing multiple block transfer capability for each transmission or reception so that the communications processor can be commanded to transfer bits, bytes or blocks of data and to indicate that such transfers have been completed by the communications processor through the generation of an interrupt. It is further desirable to tailor the communications processor to the performance of the communications task thereby minimizing the overhead introduced by somewhat standard central processors when employed in communications processors, thereby increasing the speed of the system and providing other desirable capabilities in the system. Thus it is desirable to include programs which are shareable by the various line disciplines. Further, it is desirable to improve the throughput, i.e., minimize the time required to transfer (receive or transmit) data, and to insure that one communication line does not take an excessive amount of the allotted communications time in functioning in its receive or transmit mode.
It is accordingly a primary object of the invention to provide an improved programmable communications processor for use in a data processing system.